Switchtec Userspace PROJECT_NUMBER = 4.2
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diag.h
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1/*
2 * Microsemi Switchtec(tm) PCIe Management Library
3 * Copyright (c) 2021, Microsemi Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included
13 * in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#ifndef LIBSWITCHTEC_DIAG_H
26#define LIBSWITCHTEC_DIAG_H
27
28#include <stdint.h>
29
36 uint8_t port_id;
37 uint8_t lane_id;
38 uint16_t resvd;
39};
40
42 uint8_t port_id;
43 uint8_t lane_id;
44 uint8_t ctle;
45 uint8_t target_amplitude;
46 uint8_t speculative_dfe;
47 int8_t dynamic_dfe[7];
48};
49
50enum {
51 DIAG_PORT_EQ_STATUS_OP_PER_PORT = 0,
52 DIAG_PORT_EQ_STATUS_OP_PER_LANE = 1,
53};
54
56 uint8_t sub_cmd;
57 uint8_t op_type;
58 uint8_t port_id;
59 uint8_t lane_id;
60};
61
63 uint8_t sub_cmd;
64 uint8_t port_id;
65 uint8_t lane_id;
66 uint8_t resvd;
67};
68
70 uint8_t sub_cmd;
71 uint8_t op_type;
72 uint8_t port_id;
73 uint8_t lane_id;
74
75 struct {
76 uint8_t pre;
77 uint8_t post;
78 } cursors[16];
79};
80
82 uint8_t sub_cmd;
83 uint8_t port_id;
84 uint8_t lane_id;
85 uint8_t step_cnt;
86 struct {
87 uint8_t pre_cursor;
88 uint8_t post_cursor;
89 uint8_t fom;
90 uint8_t pre_cursor_up;
91 uint8_t post_cursor_up;
92 uint8_t error_status;
93 uint8_t active_status;
94 uint8_t speed;
95 } steps[126];
96};
97
99 uint8_t sub_cmd;
100 uint8_t port_id;
101 uint8_t lane_id;
102 uint8_t fs;
103 uint8_t lf;
104 uint8_t resvd[3];
105};
106
108 uint8_t sub_cmd;
109 uint8_t port_id;
110 uint8_t lane_id;
111 uint8_t resvd;
112};
113
115 uint8_t sub_cmd;
116 uint8_t op_type;
117 uint8_t port_id;
118 uint8_t lane_id;
119};
120
122 uint8_t port_id;
123 uint8_t lane_id;
124 uint16_t ctle2_rx_mode;
125 uint8_t dtclk_9;
126 uint8_t dtclk_8_6;
127 uint8_t dtclk_5;
128};
129
131 uint8_t sub_cmd;
132 uint8_t stack_id;
133};
134
135enum switchtec_diag_loopback_type {
136 DIAG_LOOPBACK_RX_TO_TX = 0,
137 DIAG_LOOPBACK_TX_TO_RX = 1,
138};
139
141 uint8_t sub_cmd;
142 uint8_t port_id;
143 uint8_t enable;
144 uint8_t type;
145};
146
148 uint8_t port_id;
149 uint8_t enabled;
150 uint8_t type;
151 uint8_t resvdd;
152};
153
155 uint8_t sub_cmd;
156 uint8_t port_id;
157 uint8_t enable;
158 uint8_t speed;
159};
160
162 uint8_t port_id;
163 uint8_t enabled;
164 uint8_t speed;
165 uint8_t resvd;
166};
167
169 uint8_t sub_cmd;
170 uint8_t port_id;
171 uint8_t pattern_type;
172 uint8_t lane_id;
173};
174
176 uint8_t sub_cmd;
177 uint8_t port_id;
178 uint16_t resvd;
179 uint32_t err_cnt;
180};
181
183 uint8_t port_id;
184 uint8_t pattern_type;
185 uint16_t resvd;
186 uint32_t err_cnt_lo;
187 uint32_t err_cnt_hi;
188};
189
191 uint8_t sub_cmd;
192 uint8_t resvd1[3];
193 uint32_t resvd2;
194 uint32_t lane_mask[4];
195 int16_t x_start;
196 int16_t y_start;
197 int16_t x_end;
198 int16_t y_end;
199 uint16_t x_step;
200 uint16_t y_step;
201 uint32_t step_interval;
202};
203
205 uint8_t sub_cmd;
206 uint8_t data_mode;
207 uint8_t resvd;
208 uint8_t status;
209};
210
212 uint8_t sub_cmd;
213 uint8_t data_mode;
214 uint8_t resvd1;
215 uint8_t status;
216 uint32_t time_remaining;
217 uint32_t lane_mask[4];
218 uint8_t x_start;
219 uint8_t resvd2;
220 int16_t y_start;
221 uint8_t data_count_lo;
222 uint8_t frame_status;
223 uint8_t resvd3;
224 uint8_t data_count_hi;
225 union {
226 struct {
227 uint32_t error_cnt_lo;
228 uint32_t error_cnt_hi;
229 uint32_t sample_cnt_lo;
230 uint32_t sample_cnt_hi;
231 } raw[62];
232 struct {
233 uint16_t ratio;
234 } ratio[496];
235 };
236};
237
239 uint8_t sub_cmd;
240 uint8_t lane_id;
241 uint8_t all_lanes;
242 uint8_t num_lanes;
243};
244
246 uint8_t lane_id;
247 uint8_t state;
248
249 union {
250 struct {
251 int8_t byte0;
252 int8_t byte1;
253 int16_t word0;
254 int16_t word1;
255 int16_t word2;
256 int16_t word3;
257 };
258 struct {
259 uint8_t prev_state;
260 uint8_t _byte1;
261 int16_t x_pos;
262 int16_t y_pos;
263 };
264 struct {
265 int8_t eye_left_lim;
266 int8_t eye_right_lim;
267 int16_t eye_bot_left_lim;
268 int16_t eye_bot_right_lim;
269 int16_t eye_top_left_lim;
270 int16_t eye_top_right_lim;
271 };
272 };
273};
274
275#endif